1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly, to an array substrate for a liquid crystal display device and a manufacturing method thereof.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) device includes two substrates that are spaced apart and face each other with a liquid crystal material layer interposed between the two substrates. Each of the substrates includes electrodes that face each other, wherein a voltage applied to each electrode induces an electric field between the electrodes and within the liquid crystal material layer. Alignment of liquid crystal molecules of the liquid crystal material layer is changed by varying an intensity or direction of the applied electric field. Accordingly, the LCD device displays an image by varying light transmissivity through the liquid crystal material layer in accordance with the arrangement of the liquid crystal molecules.
FIG. 1 is an enlarged perspective view of a liquid crystal display (LCD) device according to the related art. In FIG. 1, an LCD device 7 has upper and lower substrates 5 and 9, which are spaced apart from and facing each other, and a liquid crystal material layer 90 interposed between the upper and lower substrates 5 and 9. The upper substrate 5 includes a black matrix 2, a color filter layer 1, and a transparent common electrode 18 subsequently disposed on an interior surface thereof. The black matrix 2 includes openings having one of three sub-color filters of red (R), green (G), and blue (B).
A gate line 11 and a data line 36 are formed on an interior surface of the lower substrate 9, which is commonly referred to as an array substrate, such that the gate line 11 and the date line 36 cross each other to define a pixel area P. In addition, a thin film transistor T is formed at the crossing of the gate line 11 and the data line 36 and includes a gate electrode, a source electrode, and a drain electrode. A pixel electrode 53 is formed within the pixel area P to correspond to the sub-color filters (R), (G), and (B), and is electrically connected to the thin film transistor T. The pixel electrode 53 is made of a light transparent conductive material, such as indium-tin-oxide (ITO).
A scanning pulse is supplied to the gate electrode of the thin film transistor T along the gate line 11, and a data signal is supplied to the source electrode of the thin film transistor T along the data line 36. Accordingly, light transmission through the liquid crystal material layer 90 is adjusted by controlling electrical and optical properties of the liquid crystal material layer 90. For example, the liquid crystal material layer 90 includes a dielectric anisotropic material having spontaneous polarization properties such that the liquid crystal molecules form a dipole when the electric field is induced. Thus, the liquid crystal molecules of the liquid crystal material layer 90 are controlled by the applied electric field. In addition, optical modulation of the liquid crystal material layer 90 is adjusted according to the arrangement of the liquid crystal molecules. Therefore, images of the LCD device are produced by controlling light transmittance of the liquid crystal material layer 90 due to optical modulation of the liquid crystal material layer 90.
FIG. 2 is a plan view of an array substrate for an LCD device according to the related art, FIG. 3 is an enlarged plan view of region “A” of FIG. 2 according to the related art, FIG. 4 is an enlarged plan view of region “B” of FIG. 2 according to the related art, and FIG. 5 is an enlarged plan view of region “C” of FIG. 2 according to the related art.
In FIG. 2, gate lines 11 and data lines 36 are formed on a substrate 9 to cross each other, thereby defining pixel areas P. A thin film transistor T (in FIG. 5) is formed at the crossing of each of the gate and data lines 11 and 36 to function as a switching element. The thin film transistor T includes a gate electrode 13 that is connected to the gate line 11 to receive scanning signals, a source electrode 33 is connected to the data line 36 and receives data signals, and a drain electrode 35 is spaced apart from the source electrode 33. In addition, the thin film transistor T includes an active layer 49 between the gate electrode 13 and the source and drain electrodes 33 and 35, and a transparent pixel electrode 53 is formed in the pixel area P and is connected to the drain electrode 35.
In FIG. 3, a gate pad 15 is formed at one end of the gate line 11, and a gate pad terminal 60 overlaps the gate pad 15. The gate pad terminal 60 may be formed of the same material as the pixel electrode 53. The gate pad 15 includes odd and even gate pads 15a and 15b, wherein the odd gate pad 15a is connected to a first shorting bar 17 and the even gate pad 15b is connected to a second shorting bar 37.
In FIG. 4, a data pad 38 is formed at one end of the data line 36, and a data pad terminal 62 overlaps the data pad 38. The data pad terminal 62 may be formed of the same material as the pixel electrode 53. The data pad 38 also includes odd and even data pads 38a and 38b, wherein the odd data pad 38a is connected to a third shorting bar 19 and the even data pad 38b is connected to a fourth shorting bar 39.
In FIGS. 3 and 4, the first to fourth shorting bars 17, 37, 19, and 39 are electrically connected to first, second, third, and fourth test pads 21, 41, 23 and 43 (in FIG. 2) through first, second, third, and fourth connecting lines 20, 45, 25 and 47 (in FIG. 2), respectively. The first, second, third, and fourth test pads 21, 41, 23, and 43 are formed along a line on a portion of the substrate 9. The first and third shorting bars 17 and 19 are made of the same material as the gate line 11, and the second and fourth shorting bars 37 and 39 are formed of the same material as the data line 36. Furthermore, the first and third test pads 21 and 23 are made of the same material as the gate line 11, and the first and third connecting lines 20 and 25 are formed of the same material as the data line 36. Accordingly, the even gate pad 15b is electrically connected to the second shorting bar 37 through the gate pad terminal 60, and the even data pad 38b is electrically connected to the fourth shorting bar 39 through the data pad terminal 62. In addition, the shorting bars 17, 37, 19, and 39 are removed by cutting the substrate 9 after the testing process of the array substrate.
FIGS. 6A to 6F are cross sectional views of a manufacturing method of the array substrate using four masks along VI-VI of FIG. 5 according to the related art, and FIGS. 7A to 7F are cross sectional views of a manufacturing method of the array substrate using four masks along VII-VII of FIG. 2 according to the related art.
In FIGS. 6A and 7A, a gate electrode 13 is formed on a substrate 9 by depositing a first metal layer, and patterning the first metal layer through a first mask process. In addition, a gate line 11 (in FIG. 5) and a gate pad 15 (in FIG. 3) are also formed on the substrate 9. Next, a gate insulating layer 29, an amorphous silicon layer 30, a doped amorphous silicon layer 31, and a second metal layer 32 are subsequently deposited on the substrate 9 and the gate electrode 13. In addition, a photoresist layer 70 is formed on the second metal layer 32 by coating a photoresist material. The gate insulating layer 29 is made of an inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiO2), and the second metal layer 32 may be formed of chromium (Cr) or molybdenum (Mo).
In FIGS. 6B and 7B, a mask 80 includes a blocking portion M1, a half transmitting portion M2, and a transmitting portion M3 that are disposed over the photoresist layer 70, wherein the blocking portion M1 corresponds to a source drain region D and the half transmitting portion M2 corresponds to a channel region E. The photoresist layer 70 may be a positive type, wherein a portion exposed to light is developed and removed. Subsequently, the photoresist layer 70 is exposed to light such that the portion of the photoresist layer 70 corresponding to the half transmitting portion M2 is exposed to the light in an amount less than the photoresist layer 70 corresponding to the transmitting portion M3. The half transmitting portion M2 may include slits or semitransparent layer.
In FIGS. 6C and 7C, the exposed photoresist layer 70 (in FIGS. 6B and 7B) is developed, whereby a photoresist pattern 72 having different thicknesses is formed. A first thickness photoresist pattern 72a corresponds to the blocking portion M1 (in FIGS. 6B and 7B) and a second thickness photoresist pattern 72b, which is thinner than the first thickness 72a, corresponds to the half transmitting portion M2 (in FIG. 6B). In addition, there is no photoresist pattern in a region corresponding to the transmitting portion M3 (in FIGS. 6B and 7B).
In FIGS. 6D and 7D, the second metal layer 32, the doped amorphous silicon layer 31, and the amorphous silicon layer 30 (of FIGS. 6C and 7C) that have been exposed by the photoresist pattern 72 are patterned, and the photoresist pattern 72 is removed. Thus, source and drain electrodes 33 and 35, an ohmic contact layer 51, an active layer 49, and a fourth connecting line 47 (also in FIG. 2) are formed through a second mask process using the mask 80 (in FIGS. 6B and 7B). Accordingly, in FIG. 7D, an amorphous silicon pattern 30a and a doped amorphous silicon pattern 31a are also formed under the fourth connecting line 47.
In FIGS. 6E and 7E, a passivation layer 56 is formed on the source and drain electrodes 33 and 35 and the fourth connecting line 47 by coating a transparent organic material, such as benzocyclobutene (BCB) and an acrylic resin, or by depositing an inorganic material, such as silicon nitride (SiNx) and silicon oxide (SiO2). Next, in FIG. 6E, the passivation layer 56 is patterned through a third mask process, thereby forming a drain contact hole 58 that exposes a portion of the drain electrode 35.
In FIG. 6F, a pixel electrode 53 is formed on the passivation layer 56 by depositing a transparent conductive material, such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO), and patterning the transparent conductive material through a fourth mask process. The pixel electrode 53 is connected to the drain electrode 35 via the drain contact hole 58.
Alternatively, the second mask process progresses differently depending on a material of the second metal layer 32 (in FIGS. 6C and 7C), such as chromium and molybdenum. The second mask process according to the chromium material will be described hereinafter with reference to figures.
FIGS. 8A to 8C are cross sectional views of a second mask process of the array substrate along VI-VI of FIG. 5 according to the related art, and FIGS. 9A to 9C are cross sectional views of a second mask process of the array substrate along VII-VII of FIG. 2 according to the related art.
In FIGS. 8A and 9A, the second metal layer 32, the doped amorphous silicon layer 31, and the amorphous silicon layer 30 (in FIGS. 6C and 7C) that have been exposed by the photoresist pattern 72 (in FIGS. 6C and 7C) are removed. The second metal layer 32 (in FIGS. 6C and 7C) that is made of chromium is etched by a wet etching method, and the doped amorphous silicon layer 31 and the amorphous silicon layer 30 (in FIGS. 6C and 7C) are patterned by a dry etching method. Thus, a source and drain pattern 32a, a doped amorphous silicon pattern 51a, an active layer 49, and a fourth connecting line 47 are formed. Next, the second thickness photoresist pattern 72b (in FIG. 6C) corresponding to the channel region “E” is removed through an ashing process, whereby exposing a portion of the source and drain pattern 32a. Accordingly, the first thickness photoresist pattern 72a is partially removed, thereby reducing the thickness of the first thickness photoresist pattern 72a. 
In FIGS. 8B and 9B, the source and drain pattern 32a (in FIG. 8A) is wet-etched by using the first thickness photoresist pattern 72a as an etching mask. Accordingly, in FIG. 8B, source and drain electrodes 33 and 35 are formed, and a portion of the doped amorphous silicon pattern 51a is exposed.
In FIGS. 8C and 9C, the doped amorphous silicon pattern 51a (in FIG. 8B) that is exposed by the source and drain electrodes 33 and 35 is dry-etched. Thus, an ohmic contact layer 51 is formed. In addition, in FIGS. 6D and 7D, the remaining photoresist pattern 72a (in FIGS. 8C and 9C) is removed. Thus, if the second metal layer 32 (of FIGS. 6C and 7C) is made of chromium, the second mask process is composed of a first wet-etch step, a first dry-etch step, a second wet-etch step, and a second dry-etch step. Accordingly, total manufacturing time increases.
Alternatively, the second metal layer 32 (in FIGS. 6C and 7C) may be formed of molybdenum, and can be dry-etched. The second mask process according to the molybdenum material will be described hereinafter with reference to figures.
FIGS. 10A and 10B are cross section views of another second mask process of the array substrate along VI-VI of FIG. 5 according to the related art, and FIGS. 11A and 11B are cross sectional views of another second mask process of the array substrate along VII-VII of FIG. 2 according to the related art.
In FIGS. 10A and 11A, the second metal layer 32, the doped amorphous silicon layer 31, and the amorphous silicon layer 30 (in FIGS. 6C and 7C) that have been exposed by the photoresist pattern 72 (in FIGS. 6C and 7C) are removed by a dry-etching method, wherein the second metal layer 32 is made of molybdenum. Thus, a source and drain pattern 32a, a doped amorphous silicon pattern 51a, an active layer 49, and a fourth connecting line 47 are formed. Next, the second thickness photoresist pattern 72b (in FIG. 6C) is removed through an ashing process, whereby exposing a portion of the source and drain pattern 32a corresponding to the channel region “E.” At this time, the first thickness photoresist pattern 72a is partially removed, whereby the thickness of the first thickness photoresist pattern 72a is reduced.
In FIGS. 10B and 11B, the source and drain pattern 32a (in FIG. 10A) and the doped amorphous silicon layer 31a are dry-etched by using the first thickness photoresist pattern 72a as an etching mask at a time. Accordingly, source and drain electrodes 33 and 35 and an ohmic contact layer 51 are formed, and a portion of the active layer 49 is exposed. As shown in FIGS. 6D and 7D, the remained photoresist pattern 72a (of FIGS. 10B and 11B) is then removed.
However, during the ashing process, the photoresist layer in an outer area on the substrate 9, that is, the photoresist pattern 72a corresponding to the fourth connecting line 47 (in FIG. 11A) is removed at a rate faster than the photoresist pattern 72a on the source and drain pattern 32a (in FIG. 10A). In addition, as shown in FIG. 11B, a part of the fourth connecting line 47 is unintentionally removed. If molybdenum is used as the second metal layer 32 (in FIGS. 6C and 7C), manufacturing time can be reduced, but testing lines, such as shorting bars and connecting lines, may be disconnected.